This invention relates to the digital phase lock loop art and, in particular, to an information bit stream clock recovery system which incorporates an improved digital phase lock loop.
Both analog and digital phase lock loop circuitry is well known in the art. Digital phase lock loops are particularly advantageous in communication receivers adapted to decode digitally encoded information. There, information is transmitted via a digital bit stream which is synchronous to a master clock at the transmitter. To successfully decode the bit stream, a slave clock in the receiver must lock in phase to the master clock frequency. Once in lock, the slave clock frequency is utilized for data reclocking decoding, digital to analog conversion, and code detection. Also, in transceivers, the slave clock may be used as a master clock for transmission.
The digital phase lock loops known to the prior art utilize RC voltage controlled oscillators. Such prior art circuits are unacceptable due to poor stability, excessive jitter resulting from high required lock range, long access time, idling off frequency on noise, and requiring frequent adjustment. Attempts to design around these problems have previously failed due to the high resultant system cost.